1. Field of the Invention
The present invention relates to a standard cell, a standard-cell-type integrated circuit which comprises a plurality of standard cells and a wiring method thereof, and more particularly to a standard cell having a delay function in addition to functions inherent thereto, a standard-cell-type integrated circuit produced with the standard cell, and a designing method for the standard-cell-type circuit.
2. Description of the Prior Art
Conventionally, there is known a standard cell system in which various cells having fundamental functions, such as AND gates, OR gates, flip-flops, and selectors are registered in a library as standard cells, and an integrated circuit is designed using them.
Arrangement of a plurality of the standard cells onto a chip and wiring among them are carried out using a computer as mentioned below.
As compared with a case in which a gate array system is used, a standard-cell-type integrated circuit which is designed and produced by this standard cell system can realize a high degree of freedom in design, reduction of chip area, a low production cost, various system functions on one chip, and the like.
On the other hand, it takes a relatively long time to develop the standard-cell-type integrated circuit as compared with the case of a gate array system.
In the standard-cell-type integrated circuit according to the conventional system, each standard cell (hereinafter called a cell) is arranged parallel in a row as shown in FIG. 6 and a width of the cell is determined by the cell. Therefore the width can not be changed.
In FIG. 6 each space between each adjacent pair of the cell rows is used for wiring therebetween. At an upper periphery, a lower periphery or an intermediate portion of each the cell is provided with an input-output terminal for each signal. A predetermined logic function is realized by connecting the respective terminals in the wiring area.
However, the conventional standard-cell-type integrated circuit causes the following problem.
Since the integrated circuit comprises a combination of a plurality of standard cells, a signal propagation delay occurs in each gate and each signal wire even though there is no error in the logic design itself. Therefore, the so-obtained integrated circuit may operate incorrectly.
Accordingly, a delay circuit should be suitably inserted in such a conventional integrated circuit for prevention of incorrect operation caused by signal propagation delay, thereby compensating for the delay and matching signal propagation.
FIG. 1 shows a portion of a shift register which is composed of a series connection of flip-flops 1 and 2. FIG. 2 shows a timing chart in a case in which the shift register shown in FIG. 1 is operated ideally. In practice, a propagation delay of a clock signal occurs, for example, in a clock wire 3 for transmitting a clock signal. FIG. 3 shows a timing chart at each terminal when the propagation delay of the clock signal occurs. The clock signals CK1 and CK2 should be inputted in the flip-flops 1 and 2 at the same time respectively. However, since the propagation delay occurs in the clock wire 3, the clock signal CK2 is inputted in the flip-flop 2 later than the clock signal CK1. Thus, incorrect wrong operation occurs.
In order to avoid the occurrence incorrect operation caused by the signal delay, a delay circuit 4 is inserted between an output terminal Q1 of the flip-flop 1 and an input terminal D2 of the flip-flop 2 as shown in FIG. 4. FIG. 5 is a timing chart to show an operation of the shift register shown in FIG. 4. When the register is composed as mentioned above, the propagation delay of the clock signal in the clock wire 3 can be compensated.
As a method of inserting the delay circuit into the integral circuit, there is known a method in which a cell having only a delay function is registered in a library, and then the cell is inserted in a predetermined location.
FIG. 6 shows a composition of a cell arrangement which realizes the circuit shown in FIG. 4 in accordance with the method mentioned above. A delay function standard cell 5 in the same drawing corresponds to the delay circuit 4 in FIG. 4. Standard cells 6 and 7 correspond to the flip-flops 1 and 2 respectively.
FIGS. 7 and 8 are circuit compositional diagrams of the standard cells 5 and 6 respectively. FIG. 7 illustrates a detailed circuit diagram for implementing a time delay using a resistor RR, a capacitor CC, and gates 71 and 72. FIG. 8 illustrates a detailed circuit diagram for implementing a flip-flop using gates 81 through 90.
In the design of the standard-cell-type integrated circuit, the arrangement of each standard cell on a real chip and the wiring among them are determined by using CAD (Computer Aided Design). When CAD is used, labor is reduced.
In order to facilitate a function test which is conducted after the design of the integrated circuit, a test circuit having a predetermined function is added in the integrated circuit. There are various compositional methods and testing methods for a test-facilitated integrated circuit. For example, the methods include the serial scan method and the LSSD (Level Sensitive Scan Design) method.
However, the above-mentioned methods cause the following problem.
A delay function is registered in a library as a cell, and then automatic placement and routing is carried out using a computer. The so-obtained layout presents a mode, for example, as shown in FIG. 6. In this case, the wiring length from the flip-flop cell 6 to the flip-flop cell 7 through the delay cell 5 depends on the position of the delay cell 5. However, the position of the delay cell 5 is not decided until automatic placement and routing of the cell is carried out. Accordingly, the degree of signal delay and the effect of the delay cell cannot be estimated because the wiring length is not decided before the automatic placement and routing.
Moreover, when delay compensation is not carried out correctly, for example, when a delay time owing to the delay cell is longer than estimated, the operation speed of the integrated circuit becomes lowered. Additionally, since the delay cell is provided anew, the chip area must be enlarged.
The problem which occurs during the function test of the test-facilitated integrated circuit, that is, the signal delay caused by gates and wires, occurs and incorrect operation results. Thus, a predetermined function test cannot be carried out in this case.
FIG. 9 is a partial view of a test-facilitated standard-cell-type integrated circuit based on the serial scan system. In the same drawing, reference numeral 8 and 9 denote flip-flop standard cells. Reference numeral 10 denotes a combinational logic circuit. The flip-flop standard cells 8 and 9 have terminals S1 and S2 for inputting scan signals during the function test respectively.
Output signals of the standard cell 8 are inputted into an input terminal D2 of the standard cell 9 through the logic circuit 10 (channel 8a), and directly into a scan signal input terminal S2 of the standard cell 9 (channel 8b).
The combination of the standard cells 8 and 9 composes a shift register. When the flip-flops are connected in the integrated circuit as shown in the drawing, the content and the state of each of the flip-flops (standard cells 8 and 9) can be read and written into an external portion at the time of the function test.
However, in the circuit shown in FIG. 9, some output signals are transmitted from the output terminal Q1 of the standard cell 8 to the input terminal S2 of the standard cell 9 without passing through the combinational logic circuit 10 during the test. Therefore, when a signal delay which occurs in the channel 8b from the output terminal Q1 to the input terminal S2 becomes shorter than another clock signal delay which occurs between the clock signal input terminal CK1 and the clock signal input terminal CK2, incorrect operation occurs. In this case, the function test cannot be carried out correctly.
Moreover, incorrect operation is also caused by the clock signal propagation delay between the cells 8 and 9 as mentioned above.